Wafer level embedded and stacked die power system-in-package packages
US8247269B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2011 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Jun 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer level embedded and stacked die power system-in-package semiconductor devices, and methods for making and using the same, are described. The methods include placing a first side of a substrate frame, which includes through cavity and an adjacent via, on a carrier. A first side of a component selected from an active device and a passive device can be placed on the carrier, within the cavity. A perimeter of the cavity can be attached to a perimeter of the component. Material at a second side of the substrate frame can be removed so the via extends from the frame's first side to the frame's second side. The substrate frame and component can then be removed from the carrier so that routing can be distributed between the first side of the frame and the first side of the component to electrically connect the component with the via. Other embodiments are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.