Method for fabricating a transistor including a polysilicon layer formed using two annealing processes
US8247316B2 · kind B2 · utility
0Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | May 13, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.