Via/contact and damascene structures and manufacturing methods thereof
US8247322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2007 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Jul 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.