Frequency compression for an interleaved power factor correction (PFC) converter
US8248041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A controller provides frequency compression for an interleaved power factor correction (PFC) converter that determines the ON and OFF times of each switch associated with the PFC converter to prevent operating frequencies in the audible range. The controller includes a first circuit for generating an ON time current source having a magnitude related to an amplified error signal and the monitored input voltage, and a second circuit for generating an OFF time current source having a magnitude related to the ON time current source, the monitored input voltage, and the monitored output voltage. Gate drive circuitry provides gate drives signals to the switches of the interleaved PFC converter at a frequency determined by magnitudes of the ON time current source and the OFF time current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.