Semiconductor device having hierarchically structured bit lines and system including the same
US8248834B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Feb 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.