System and methods for multi-level nonvolatile memory read, program and erase
US8248848B1 · kind B1 · utility
10Cited by
12References
43Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a memory array with multi-level cells that are each capable of storing M bits of data, where M is an integer greater than one. A module reads a state of one of the multi-level cells. The module performs at least one of a first erase operation and a first program operation on the one of the multi-level cells for the M bits of data during a first time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.