Semiconductor memory apparatus and probe test control circuit therefor
US8248874B2 · kind B2 · utility
1Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed probe test control circuit includes: a bank active circuit configured to generate a bank active signal in response to a bank address and bank-by-bank test control signals; and a mat active circuit configured to generate a mat-by-mat sub-wordline selection signal and provide the mat-by-mat sub-wordline selection signal to a selected memory bank, in response to a row address signal, a row address enable signal and a mat-by-mat test control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.