Cache coherency protocol with built in avoidance for conflicting responses
US8250308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Apr 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.