Hardware wake-and-go mechanism for a data processing system
US8250396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2008 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Oct 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.