Parallel process optimized signal routing
US8250513B1 · kind B1 · utility
7Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Nov 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.