Method for thinning a wafer
US8252682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Dec 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/02372
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.