Structures for lowering trigger voltage in an electrostatic discharge protection device
US8253165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.