MOS transistor with gate trench adjacent to drain extension field insulation

US8253193B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Marie Denison · Plano, US
• Sameer Pendharkar · Allen, US
• Binghua Hu · Plano, US
• Taylor R. Efland · Richardson, US
• Sridhar Seetharaman · Richardson, US

Key dates

• Filing date: Jan 14, 2011
• Grant date: Aug 28, 2012
• Expiry date: Jan 14, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.