Brown-out detection circuit
US8253453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jan 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.