Delay locked loop circuit and operation method thereof
US8253455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jan 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.