Digital phase locked loop with reduced switching noise
US8253458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2011 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.