Memory controller interface for micro-tiled memory access
US8253751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.