Semiconductor memory device having pad electrodes arranged in plural rows
US8254153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.