User-level interrupt mechanism for multi-core architectures
US8255603B2 · kind B2 · utility
5Cited by
3References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 8, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/1881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.