Flexible sequence design architecture for solid state memory controller
US8255615B1 · kind B1 · utility
8Cited by
1References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and computer program products for sending one or more commands to one or more flash memory devices using a solid state controller and receiving information associated with the commands from the flash memory devices are described. In some implementations, the solid state controller includes a sequencer to forward the commands to the flash memory devices on behalf of the firmware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.