System and method for generating flat layout
US8255845B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Sep 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.