Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit
US8255854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.