Patent · US Active

Redundant clock channel for high reliability connectors

US8257092B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sungjun Chun · Austin, US
Daniel M. Dreps · Georgetown, US
Dierk Kaller · Schenefeld, DE
Rohan U. Mandrekar · Austin, US
Lei Shan · Carmel, US

Key dates

Filing date	Nov 15, 2010
Grant date	Sep 4, 2012
Priority date	—
Expiry date	Nov 15, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.