Fabrication of a vertical heterojunction tunnel-FET
US8258031B2 · kind B2 · utility
14Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Nov 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/211
Abstract
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.