Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers

US8258053B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stephan Kronholz · Dresden, DE
• Matthias Kessler · Dresden, DE
• Andreas Kurz · Oberursel, DE

Key dates

• Filing date: Oct 8, 2010
• Grant date: Sep 4, 2012
• Expiry date: Dec 1, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.