Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
US8259494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Aug 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.