Self-refresh test circuit of semiconductor memory apparatus
US8259527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Oct 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.