Patent · US Active

Self power down integrated circuit

US8261101B1 · kind B1 · utility

3Cited by
11References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 31, 2008
Grant dateSep 4, 2012
Priority date
Expiry dateApr 5, 2031

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.