System and method for optimized error correction in flash memory arrays
US8261124B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Jan 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks that can be associated with the data blocks, wherein data blocks and the redundancy blocks can be assembled into a data stripe that can be stored in three or more of the memory components. Upon retrieval of the data stripe, the optimal correction component, an error correction code (ECC) component or a combination thereof can correct data blocks that contain errors wherein the decision whether the optimized correction component or the error correction code (ECC) component corrects the errors can be based in part on a predetermined criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.