Error management watchdog timers in a multiprocessor computer
US8261134B2 · kind B2 · utility
4Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Jan 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0852
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.