High-yield method of exposing and contacting through-silicon vias
US8263497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2009 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Dec 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.