Merged cascode transistor
US8264003B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Mar 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element. The first gate is connected to an input voltage signal such that conduction of the first portion is based on a value of the input voltage signal and the second gate is connected to a predetermined constant voltage such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at the source electrode reaches a predetermined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.