Symmetric STT-MRAM bit cell design
US8264052B2 · kind B2 · utility
4Cited by
3References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.