Techniques for asynchronous data recovery
US8265216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jul 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.