Patent · US Active

Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance

US8266411B2 · kind B2 · utility

0Cited by

8References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Gemmeke · Santa Clara, US
Markus Kaltenbach · Holzgerlingen, DE
Nicolas Maeding · Holzgerlingen, DE

Key dates

Filing date	Feb 5, 2009
Grant date	Sep 11, 2012
Priority date	—
Expiry date	Feb 25, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3861
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.