Pattern generating method, method of manufacturing semiconductor device, and recording medium
US8266552B2 · kind B2 · utility
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3References
18Claims
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Key dates
| Filing date | Feb 15, 2010 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Dec 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.