Vertical junction field effect transistor with mesa termination and method of making the same
US8269262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2007 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Aug 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.