Complementary semiconductor device with a metal oxide layer exclusive to one conductivity type
US8269286B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A method is provided of manufacturing a semiconductor device comprising a first, n-type field effect transistor (1) and a second, p-type field effect transistor (2). The method comprises depositing a gate dielectric layer over a substrate; depositing a gate metal layer (22) over the gate dielectric layer, depositing a solid metal oxide layer (15) over the gate dielectric layer; removing a portion of the solid metal oxide layer (15) over an area of the substrate corresponding to the n-type transistor; and completing gate stacks for the n-type and p-type transistors and forming source and drain regions. The invention thus provides a device which is compatible with IC technology and easy to manufacture. The deposition of a solid metal oxide layer provides a simplified manufacturing process, by avoiding the complexity of gas exposure to form an oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.