Packaging substrate having through-holed interposer embedded therein and fabrication method thereof
US8269337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2011 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10515
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.