Testing state retention logic in low power systems

US8271226B2 · kind B2 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Krishna Vijaya Chakravadhanula · Vestal, US
• Patrick Gallagher · Apalachin, US
• Vivek Chickermane · Ithaca, US
• Steven Lee Gregor · Owego, US
• Puneet Arora · Noida, IN

Key dates

• Filing date: Jun 26, 2008
• Grant date: Sep 18, 2012
• Expiry date: Nov 3, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318575
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.