Handling of write access requests to shared memory in a data processing apparatus
US8271730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2007 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Sep 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.