Patent · US Active

Apparatus for operating cache-inhibited memory mapped commands to access registers

US8271738B2 · kind B2 · utility

5Cited by

8References

9Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

James Stephen Fields, Jr. · Austin, US
Michael Stephen Floys · Austin, US
Paul Frank Lecocq · Cedar Park, US
Larry Scott Leitner · Austin, US
Kevin F. Reick · Austin, US

Key dates

Filing date	May 2, 2008
Grant date	Sep 18, 2012
Priority date	—
Expiry date	Jan 24, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0888
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.