Patent · US Active

Integrated circuit arrangement including vias having two sections, and method for producing the same

US8273658B2 · kind B2 · utility

1Cited by

6References

14Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Klaus Goller · Dresden, DE
Jakob Kriz · Ochtrup, DE

Key dates

Filing date	Aug 25, 2005
Grant date	Sep 25, 2012
Priority date	—
Expiry date	Oct 10, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.