Equalization circuit
US8274326B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Oct 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.