Write and erase scheme for resistive memory device
US8274812B2 · kind B2 · utility
60Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Jun 14, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Jan 3, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.