Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US8274849B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 2011 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | May 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.