Software table walk during test verification of a simulated densely threaded network on a chip
US8275598B2 · kind B2 · utility
5Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2009 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Mar 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.