Parallel memory device rank selection
US8275956B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Jun 24, 2011 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.