Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
US8276051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2008 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Oct 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.