Spatial correlation-based estimation of yield of integrated circuits
US8276102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Dec 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.